Engineering the Electron-Hole Bilayer Tunneling Field- Effect Transistor

Novel attributes of steep-slope staggered type heterojunction p-channel electron-hole bilayer tunnel field effect transistor

In this paper, the electrical characteristics and sensitivity analysis of staggered type p-channel heterojunction electron-hole bilayer tunnel field effect transistor (HJ-EHBTFET) are thoroughly investigated via simulation study. The minimum lattice mismatch between InAs/GaAs0.1Sb0.9 layers besides low carrier effective mass of materials provides high probability ...

Comment on ‘Germanium electron–hole bilayer tunnel field-effect transistors with a symmetrically arranged double gate’

In this comment we demonstrate that the inclusion of field-induced quantum confinement effects through appropriate discretization of conduction and valence bands refutes the suitability of a germanium electron–hole bilayer tunnel field-effect transistor with symmetrically arranged gates (Jeong et al 2015 Semicond. Sci. Technol. 30 035021). Delayed alignment of the first electron and hole energy...

Assessment of pseudo-bilayer structures in the heterogate germanium electron-hole bilayer tunnel field-effect transistor

Performance Study and Analysis of Heterojunction Gate All Around Nanowire Tunneling Field Effect Transistor

In this paper, we have presented a heterojunction gate all around nanowiretunneling field effect transistor (GAA NW TFET) and have explained its characteristicsin details. The proposed device has been structured using Germanium for source regionand Silicon for channel and drain regions. Kane's band-to-band tunneling model hasbeen used to account for the amount of band-to...

Analysis and study of geometrical variability on the performance of junctionless tunneling field effect transistors: Advantage or deficiency?

This study investigates geometrical variability on the sensitivity of the junctionless tunneling field effect transistor (JLTFET) and Heterostructure JLTFET (HJLTFET) performance. We consider the transistor gate dielectric thickness as one of the main variation sources. The impacts of variations on the analog and digital performance of the devices are calculated by using computer aided design (...